Risk Assessment & Management Flashcards
7 cards from real PCB practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 Risk Assessment & Management flashcards as text
What risk does insufficient clearance between high-voltage traces on a PCB introduce?
Answer: Dielectric breakdown and arcing between conductors
Insufficient high-voltage clearance can cause dielectric breakdown through air or substrate, resulting in arcing and catastrophic failure.
A PCB design uses a star ground topology for a mixed-signal board. What risk does this topology help mitigate?
Answer: Ground loops that allow noise currents to couple between analog and digital sections
Star grounding ensures that ground return currents from digital and analog circuits share no common impedance, preventing noise coupling.
Which manufacturing risk is introduced by specifying a minimum annular ring that is too small for the fabrication process capability?
Answer: Drill breakout that disconnects the via pad from the drilled hole, causing open circuits
If annular rings are smaller than fabrication tolerances, drill registration error can break out of the pad, creating open vias.
What is the primary risk of using Ball Grid Array (BGA) components without performing X-ray inspection after soldering?
Answer: Hidden solder joint defects such as bridges, opens, or insufficient reflow cannot be detected visually
BGA solder joints are hidden under the package body, making X-ray inspection the only reliable method to detect joint defects.
What risk is created by routing a high-speed clock signal without a continuous ground reference plane beneath it?
Answer: Discontinuous return path increases loop area, worsening EMI and signal integrity
Clock signals need a low-impedance return path directly below; gaps in the reference plane force return currents to take longer paths, increasing EMI.
During component placement, a designer positions a large electrolytic capacitor directly over a thermal relief pad area. What risk does this create?
Answer: Restricted rework access and possible heat stress on the capacitor during soldering of nearby components
Placing heat-sensitive components over thermal relief zones can expose them to damaging temperatures during adjacent soldering operations.
What risk is mitigated by including a keep-out zone around crystal oscillators during PCB layout?
Answer: Interference from nearby high-frequency traces or components that could destabilize the oscillator frequency
Keep-out zones around crystals prevent interference from nearby signals that could couple into the oscillator circuit and cause frequency instability.