NVIDIA-Certified Associate - Data Science — Questions and Answers

Question 1: Which layer type is commonly used in Convolutional Neural Networks (CNNs)?

Dropout layer.
Fully connected layer.
Convolutional layer (Correct answer)
Recurrent layer.

Correct answer: Convolutional layer

The convolutional layer is a core component commonly used in Convolutional Neural Networks (CNNs), especially for tasks involving image and video processing. This layer applies a set of learnable filters (kernels) to the input data, performing a convolution operation to extract features such as edges, textures, or patterns. These extracted features are then passed to subsequent layers for further processing and analysis.

Question 2: In tensor parallelism, how are transformer model layers typically partitioned across GPUs?

Each GPU holds a full copy of every layer
Attention heads are replicated identically on every GPU
Different transformer blocks are assigned to different GPUs sequentially
Weight matrices are split along one dimension so GPUs compute partial results (Correct answer)

Correct answer: Weight matrices are split along one dimension so GPUs compute partial results

Tensor parallelism shards weight matrices across GPUs so each device computes a column- or row-parallel portion of the matrix multiply.

Question 3: What distinguishes NVIDIA Nsight Compute from NVIDIA Nsight Systems?

Nsight Compute provides deep per-kernel GPU metrics; Nsight Systems delivers system-wide CPU+GPU timeline analysis (Correct answer)
Both tools perform identical analysis but target different GPU generations
Nsight Compute is for Windows only; Nsight Systems is cross-platform
Nsight Compute profiles system-wide CPU+GPU timelines; Nsight Systems analyzes individual kernel metrics

Correct answer: Nsight Compute provides deep per-kernel GPU metrics; Nsight Systems delivers system-wide CPU+GPU timeline analysis

Nsight Compute is a GPU kernel profiler providing detailed hardware counter metrics per kernel, while Nsight Systems is a system-wide performance analyzer showing CPU, GPU, and memory activity over time.

Question 4: What is a common technique to prevent overfitting?

Increasing learning rate.
Decreasing batch size.
Using only training data.
Dropout (Correct answer)

Correct answer: Dropout

Dropout is a powerful regularization technique used to prevent overfitting in neural networks. It works by randomly deactivating a percentage of neurons during each training step, forcing the network to learn more robust features and preventing over-reliance on any single neuron or specific connections. This effectively creates an ensemble of smaller networks, improving generalization.

Question 5: Which memory space in CUDA is read-only, cached, and optimized for broadcast to all threads?

Texture memory
Constant memory (Correct answer)
Local memory
Shared memory

Correct answer: Constant memory

Constant memory is a read-only, cached region optimal when all threads read the same address simultaneously.

Question 6: What distinguishes pipeline parallelism from tensor parallelism in distributed training?

Pipeline parallelism is only applicable to CNNs while tensor parallelism works with transformers
Pipeline parallelism uses multiple nodes while tensor parallelism is single-node only
Pipeline parallelism splits layers sequentially across GPUs, while tensor parallelism partitions individual layer computations (Correct answer)
Pipeline parallelism requires gradient checkpointing while tensor parallelism does not

Correct answer: Pipeline parallelism splits layers sequentially across GPUs, while tensor parallelism partitions individual layer computations

Pipeline parallelism assigns different layers to different GPUs (inter-layer), while tensor parallelism splits individual layer weight matrices across GPUs (intra-layer).

Question 7: What problem does the Adam optimizer address that vanilla SGD with momentum does not?

Adaptive per-parameter learning rates based on first and second moment estimates of gradients (Correct answer)
Gradient clipping to prevent exploding updates in deep networks
Automatic learning rate scheduling based on validation loss plateaus
Second-order curvature estimation using the Hessian matrix

Correct answer: Adaptive per-parameter learning rates based on first and second moment estimates of gradients

Adam maintains exponential moving averages of both gradients (first moment) and squared gradients (second moment) to compute adaptive per-parameter learning rates.

Question 8: Which attention mechanism variant reduces the memory complexity of self-attention from O(n²) to near-linear, benefiting long-sequence NLP tasks?

Multi-Head Attention
Cross Attention
Grouped Query Attention
Flash Attention (Correct answer)

Correct answer: Flash Attention

Flash Attention uses tiling and recomputation to avoid materializing the full N×N attention matrix, reducing memory usage to O(n) while maintaining mathematical equivalence.

Question 9: Which activation function outputs values between 0 and 1?

ReLU.
Linear.
Tanh.
Sigmoid (Correct answer)

Correct answer: Sigmoid

The Sigmoid activation function outputs values that are squashed into a range between 0 and 1. This characteristic makes it particularly useful in the output layer of binary classification problems, where the output can be interpreted as a probability. While once popular in hidden layers, its vanishing gradient problem has led to ReLU being preferred for those layers.

Question 10: What is the primary purpose of the cuDNN library in the NVIDIA software stack?

Providing optimized primitives for deep neural network operations (Correct answer)
Managing GPU memory allocation and deallocation
General-purpose dense matrix multiplication for all workloads
Enabling multi-GPU communication via collectives

Correct answer: Providing optimized primitives for deep neural network operations

cuDNN (CUDA Deep Neural Network library) provides highly tuned implementations of primitives such as convolution, pooling, normalization, and activation functions used in deep learning.

Question 11: When authenticating to the NGC container registry via Docker, which registry hostname is used?

nvcr.io (Correct answer)
registry.nvidia.com
docker.ngc.io
hub.ngc.nvidia.com

Correct answer: nvcr.io

NGC container images are hosted at nvcr.io, so Docker login and pull commands must reference this hostname.

Question 12: Which NVIDIA software platform provides a unified ecosystem of GPU-accelerated libraries, frameworks, and tools for data center AI workloads?

NVIDIA Omniverse
NVIDIA Fleet Command
NVIDIA RAPIDS only
CUDA-X AI (Correct answer)

Correct answer: CUDA-X AI

CUDA-X AI is NVIDIA's collection of GPU-accelerated libraries and SDKs (cuDNN, cuBLAS, TensorRT, etc.) that power AI and HPC workloads across data centers.

Question 13: Which of the following best describes a key competency required for inference optimization & tensorrt in NCA practice?

Reliance on a single methodology for all situations
Memorization of all relevant regulations without understanding context
The ability to work independently without any oversight
Strong analytical skills combined with effective communication and ethical judgment (Correct answer)

Correct answer: Strong analytical skills combined with effective communication and ethical judgment

NCA professionals working in inference optimization & tensorrt need analytical skills to assess situations, communication skills to convey findings, and ethical judgment to make sound decisions.

Question 14: Which NVIDIA data center GPU is specifically optimized for inference workloads with a balance of INT8 performance and low power consumption?

A100 80GB SXM4
V100 32GB
L4 (Ada Lovelace) (Correct answer)
H100 NVL

Correct answer: L4 (Ada Lovelace)

The L4 is based on Ada Lovelace architecture and is designed for energy-efficient inference, video AI, and graphics workloads with a 72W TDP.

Question 15: What does 'weak scaling' measure in a multi-GPU benchmark?

Performance when problem size is fixed and GPU count increases
Performance when problem size grows proportionally with GPU count (Correct answer)
Memory bandwidth utilization per GPU
The ratio of GPU idle time to active compute time

Correct answer: Performance when problem size grows proportionally with GPU count

Weak scaling evaluates whether throughput remains constant as both problem size and GPU count increase proportionally.

Question 16: Which type of memory has the highest latency in CUDA?

Shared memory.
Register memory.
Texture memory.
Global memory (Correct answer)

Correct answer: Global memory

Global memory has the highest latency among the commonly used CUDA memory types. It resides off-chip in the device's DRAM and is accessible by all threads across all blocks, but accessing it is significantly slower than on-chip memories like registers or shared memory. Minimizing global memory accesses and maximizing data reuse in faster memories is a critical optimization strategy in CUDA programming.

Question 17: What is a CUDA warp?

A set of thread blocks on one SM
A group of 32 threads that execute in lockstep (Correct answer)
A single thread block
A group of 64 threads that execute in lockstep

Correct answer: A group of 32 threads that execute in lockstep

A warp consists of 32 threads that are scheduled and executed together in SIMT fashion on an SM.

Question 18: Which metric best indicates that Tensor Cores are being heavily utilized in a training workload?

High sm__pipe_tensor_cycles_active percentage in Nsight Compute (Correct answer)
High PCIe transfer rate
High GPU memory bandwidth utilization
High SM occupancy alone

Correct answer: High sm__pipe_tensor_cycles_active percentage in Nsight Compute

sm__pipe_tensor_cycles_active measures the fraction of cycles where Tensor Core pipelines are active, directly indicating utilization.

Question 19: What is warp in CUDA terminology?

A block of memory.
A single thread.
Group of 32 threads (Correct answer)
A GPU core.

Correct answer: Group of 32 threads

In CUDA terminology, a warp is a fundamental unit of execution consisting of 32 threads. These 32 threads execute the same instruction in lockstep, making them highly efficient for parallel processing. The GPU hardware schedules and executes warps, not individual threads, which is a key aspect of its SIMT (Single Instruction, Multiple Thread) architecture.

Question 20: When using TensorRT's IExecutionContext for inference, which method launches asynchronous GPU execution?

context.execute_sync(bindings)
engine.forward(tensors)
run_inference(inputs)
execute_async_v2(bindings, stream_handle) (Correct answer)

Correct answer: execute_async_v2(bindings, stream_handle)

execute_async_v2 enqueues the inference work into a specified CUDA stream, enabling overlap with other GPU or CPU work.

Question 21: Which NVIDIA software stack component provides a container runtime that allows Docker containers to access GPUs?

cuDNN
CUDA Toolkit
NVIDIA Driver
NVIDIA Container Toolkit (nvidia-docker) (Correct answer)

Correct answer: NVIDIA Container Toolkit (nvidia-docker)

The NVIDIA Container Toolkit (formerly nvidia-docker2) enables Docker containers to access GPU resources through a container runtime hook.

Question 22: What is the significance of the 'ea' tag suffix on some NGC container images?

It marks an Encrypted Archive for secure distribution
It signifies an Enterprise Authorized version
It denotes an End-of-life Archived build
It indicates an Early Access release not yet fully production-ready (Correct answer)

Correct answer: It indicates an Early Access release not yet fully production-ready

The 'ea' tag suffix stands for Early Access, indicating the container is a preview release that may not be fully stable for production use.

Question 23: What is a key limitation of naive pipeline parallelism that the '1F1B' (one-forward-one-backward) schedule addresses?

Inability to use FP16 precision across pipeline stages
High memory usage from storing all micro-batch activations simultaneously during the fill phase (Correct answer)
Excessive NVLink bandwidth use during the fill phase
Gradient divergence caused by different micro-batch orderings

Correct answer: High memory usage from storing all micro-batch activations simultaneously during the fill phase

1F1B interleaves forward and backward passes of micro-batches so that activations from completed backward passes are freed before new forward passes accumulate them, bounding peak memory.

Question 24: In an edge AI camera pipeline, what does the term 'sensor fusion' refer to?

Merging firmware from multiple camera vendors
Combining data from multiple sensor modalities (e.g., RGB, lidar, radar) to produce richer scene understanding (Correct answer)
Fusing GPU and CPU processing on a single SoC
Updating camera ISP parameters via AI inference

Correct answer: Combining data from multiple sensor modalities (e.g., RGB, lidar, radar) to produce richer scene understanding

Sensor fusion integrates outputs from heterogeneous sensors to improve perception accuracy beyond what any single sensor can provide.

Question 25: Which NVIDIA Jetson module is specifically designed for entry-level edge AI applications with the lowest power envelope in the Jetson lineup?

Jetson Nano (Correct answer)
Jetson Orin NX
Jetson TX2
Jetson AGX Orin

Correct answer: Jetson Nano

Jetson Nano targets entry-level edge AI with a ~5–10W power envelope, making it ideal for cost-sensitive embedded deployments.

Question 26: A company wants to deploy GPU-accelerated Kubernetes workloads. Which NVIDIA component enables GPUs to be scheduled as resources within Kubernetes?

CUDA Toolkit only
NVIDIA TensorRT
NVIDIA GPU Operator (Correct answer)
NVIDIA DCGM Exporter

Correct answer: NVIDIA GPU Operator

The NVIDIA GPU Operator automates the deployment and management of GPU software components (drivers, CUDA, device plugin) needed for GPU-accelerated Kubernetes workloads.

Question 27: How do you specify the number of thread blocks and threads per block when launching a CUDA kernel?

With the triple angle bracket <<<grid, block>>> syntax (Correct answer)
Inside the kernel using blockDim and gridDim
Using cudaLaunchKernel() API only
Via a configuration struct passed as the first argument

Correct answer: With the triple angle bracket <<<grid, block>>> syntax

CUDA kernels are launched with kernel<<<gridDim, blockDim>>>(...) where the triple angle brackets specify the execution configuration.

Question 28: What is 'memory coalescing' in the context of NVIDIA GPU global memory access?

Prefetching data from system RAM into GPU global memory
Merging consecutive thread memory accesses into a single wide memory transaction (Correct answer)
Compressing sparse tensors before storing them to VRAM
Combining multiple L2 cache lines into a single HBM access

Correct answer: Merging consecutive thread memory accesses into a single wide memory transaction

Memory coalescing merges individual thread memory requests into a single wide memory transaction when threads in a warp access consecutive addresses, maximizing memory bandwidth utilization.

Question 29: What is the significance of the 'NVIDIA Deep Learning Frameworks' containers on NGC compared to upstream framework containers?

They replace standard Python with NVIDIA's proprietary interpreter
They include a paid license key that must be activated before use
They run exclusively on NVIDIA DGX systems and cannot be used on other hardware
They are optimized with NVIDIA-specific performance patches, cuDNN tuning, and mixed-precision support not present in upstream images (Correct answer)

Correct answer: They are optimized with NVIDIA-specific performance patches, cuDNN tuning, and mixed-precision support not present in upstream images

NGC framework containers include NVIDIA-specific optimizations such as cuDNN integration, TensorRT support, AMP tuning, and performance patches that are not in community upstream images.

Question 30: What does GPUDirect RDMA enable in a multi-node GPU cluster?

Direct data transfer between a GPU and a remote network adapter (InfiniBand/RoCE) without CPU involvement (Correct answer)
GPU-to-GPU communication exclusively over PCIe within a single node
Automatic NVLink topology configuration across nodes
Remote access to GPU kernels via the network for distributed debugging

Correct answer: Direct data transfer between a GPU and a remote network adapter (InfiniBand/RoCE) without CPU involvement

GPUDirect RDMA allows network adapters to directly read from and write to GPU memory, removing CPU copies from the inter-node communication path.

Question 31: In a multi-GPU setup, which API call is used to enable direct peer-to-peer memory access between two CUDA devices?

cudaDeviceSynchronize() across devices
cudaMemcpyPeer()
cudaSetDevice() with both device IDs
cudaDeviceEnablePeerAccess() (Correct answer)

Correct answer: cudaDeviceEnablePeerAccess()

cudaDeviceEnablePeerAccess() enables one GPU to directly read/write another GPU's memory over NVLink or PCIe without routing through host memory, reducing latency and improving bandwidth.

Question 32: When serializing a TensorRT engine with engine.serialize(), what format is the output?

A binary blob (plan file) specific to the GPU and TensorRT version used during the build (Correct answer)
A JSON configuration that can be reloaded on any GPU
A CUDA PTX assembly file
A portable ONNX model file

Correct answer: A binary blob (plan file) specific to the GPU and TensorRT version used during the build

Serialized TensorRT engines are binary plan files that are GPU-architecture-specific and not portable across different GPU generations or TensorRT versions.

Question 33: What is the effect of enabling 'workspace size' settings in TensorRT builder configuration on a Jetson device with limited DRAM?

Workspace size only affects CPU-side preprocessing and has no GPU memory impact
Increasing workspace size reduces inference latency by pre-loading model weights into L2 cache
Larger workspace allows TensorRT to explore more kernel variants during optimization but consumes more DRAM at build time (Correct answer)
Smaller workspace forces TensorRT to use FP16 precision for all layers

Correct answer: Larger workspace allows TensorRT to explore more kernel variants during optimization but consumes more DRAM at build time

A larger TensorRT workspace gives the optimizer more scratch memory to try additional kernel strategies, potentially improving performance, but at the cost of higher peak DRAM usage during engine building.

Question 34: Which CUDA compute capability version is the minimum required to use Tensor Cores?

6.0
5.3
7.0 (Correct answer)
8.0

Correct answer: 7.0

Tensor Cores were introduced with compute capability 7.0 (Volta architecture, V100).

Question 35: What is the role of the 'calibration dataset' when applying INT8 quantization in TensorRT?

It sets the learning rate for quantization-aware training
It defines the dynamic range of model outputs
It provides representative inputs to compute optimal activation scaling factors (Correct answer)
It is used to fine-tune the model weights

Correct answer: It provides representative inputs to compute optimal activation scaling factors

The calibration dataset allows TensorRT to observe real activation distributions and compute per-tensor scaling factors that minimize quantization error.

Question 36: What is the purpose of 'trtexec', the command-line tool included with TensorRT?

Benchmarking inference throughput/latency and building/testing engines without writing code (Correct answer)
Compiling CUDA kernels from ONNX models directly to PTX
Managing multiple TensorRT engines across a cluster of GPU servers
Converting TensorRT plan files to ONNX for framework re-import

Correct answer: Benchmarking inference throughput/latency and building/testing engines without writing code

trtexec is NVIDIA's reference benchmarking tool that builds TensorRT engines from ONNX models and measures throughput and latency with configurable precision and batch sizes.

Question 37: In NVIDIA GPUs, what is a 'bank conflict' in shared memory and how does it affect performance?

Multiple warps reading the same cache line in L2, causing serialized DRAM fetches
Two thread blocks competing for the same shared memory allocation on an SM
A condition where a warp stalls because its shared memory request conflicts with an L1 eviction
Multiple threads in a warp simultaneously accessing different addresses in the same shared memory bank, causing serialized access (Correct answer)

Correct answer: Multiple threads in a warp simultaneously accessing different addresses in the same shared memory bank, causing serialized access

Shared memory is divided into banks, and when multiple threads in a warp access different addresses that map to the same bank, the accesses are serialized, reducing effective shared memory bandwidth.

Question 38: What does the CUDA programming model term 'grid' refer to?

A group of 32 threads executing in lockstep
The collection of all thread blocks launched by a kernel (Correct answer)
A single thread executing on the GPU
The shared memory region of an SM

Correct answer: The collection of all thread blocks launched by a kernel

A grid is the complete set of thread blocks that are launched together when a kernel is invoked.

Question 39: In a convolutional neural network, what does the 'receptive field' of a neuron refer to?

The region of the input image that influences a particular neuron's output (Correct answer)
The total number of trainable parameters in the network
The spatial dimensions of feature maps after pooling
The number of filters in a convolutional layer

Correct answer: The region of the input image that influences a particular neuron's output

The receptive field is the spatial extent of the input that a neuron 'sees,' which grows deeper in the network through stacked convolutions.

Question 40: A CUDA kernel achieves only 40% of theoretical memory bandwidth. What is the most likely cause?

Insufficient shared memory allocation
Excessive register usage
Too many thread blocks
Uncoalesced global memory accesses (Correct answer)

Correct answer: Uncoalesced global memory accesses

Uncoalesced global memory accesses force the GPU to issue multiple memory transactions instead of one, significantly reducing effective bandwidth utilization.

Question 41: In PyTorch, what is the purpose of `torch.no_grad()` context manager?

Disables GPU acceleration
Prevents gradient computation to save memory and speed up inference (Correct answer)
Disables CUDA operations
Freezes model weights permanently

Correct answer: Prevents gradient computation to save memory and speed up inference

`torch.no_grad()` disables autograd tracking, reducing memory usage and computation during inference when gradients are not needed.

Question 42: Which of the following best describes a key competency required for tensor core & mixed precision in NCA practice?

The ability to work independently without any oversight
Memorization of all relevant regulations without understanding context
Strong analytical skills combined with effective communication and ethical judgment (Correct answer)
Reliance on a single methodology for all situations

Correct answer: Strong analytical skills combined with effective communication and ethical judgment

NCA professionals working in tensor core & mixed precision need analytical skills to assess situations, communication skills to convey findings, and ethical judgment to make sound decisions.

Question 43: What NVIDIA GPU feature enables peer-to-peer memory access between GPUs on the same node without routing data through the CPU?

CUDA Managed Memory
ECC Memory
NVLink Compression
Unified Virtual Addressing (UVA) with GPUDirect P2P (Correct answer)

Correct answer: Unified Virtual Addressing (UVA) with GPUDirect P2P

GPUDirect Peer-to-Peer allows GPUs to directly read and write each other's memory over PCIe or NVLink, bypassing the CPU and system memory.

Question 44: Which parallelism strategy in distributed training splits individual layers across multiple GPUs, with each GPU holding a subset of each layer's parameters?

Tensor parallelism (Correct answer)
Data parallelism
Expert parallelism
Pipeline parallelism

Correct answer: Tensor parallelism

Tensor parallelism (intra-layer model parallelism) partitions weight matrices across GPUs, with each GPU computing a portion of each layer's operation.

Question 45: What is the purpose of NVIDIA's Apex library in PyTorch mixed-precision training?

Enabling automatic mixed precision (AMP) with FP16/FP32 for faster training with less memory (Correct answer)
Providing distributed training primitives for multi-node clusters
Optimizing data loading pipelines for GPU transfer
Implementing custom CUDA kernels for transformer layers

Correct answer: Enabling automatic mixed precision (AMP) with FP16/FP32 for faster training with less memory

Apex provides AMP utilities including `amp.initialize()` and `amp.scale_loss()` to use FP16 computations while maintaining FP32 master weights for stability.

Question 46: Which flag passed to nvcc enables generation of PTX code for future GPU architectures not yet released at compile time?

-use_fast_math
-arch=compute_XY without -code=sm_XY to embed PTX (Correct answer)
-maxrregcount
-ptxas-options=-v

Correct answer: -arch=compute_XY without -code=sm_XY to embed PTX

Compiling with -arch=compute_XY (virtual architecture only) embeds PTX bytecode that the CUDA driver can JIT-compile to native ISA for any future GPU compatible with that compute capability.

Question 47: What is the primary role of NVIDIA NCCL in distributed deep learning?

Scheduling GPU tasks across a cluster
Compiling CUDA kernels for multiple GPU architectures
Managing GPU memory allocation across nodes
Providing optimized collective communication primitives for multi-GPU and multi-node training (Correct answer)

Correct answer: Providing optimized collective communication primitives for multi-GPU and multi-node training

NCCL (NVIDIA Collective Communications Library) provides optimized all-reduce, broadcast, and other collective operations essential for distributed training.

Question 48: Which PyTorch function enables automatic mixed precision (AMP) training with Tensor Cores?

torch.cuda.amp.autocast() (Correct answer)
torch.nn.DataParallel()
torch.enable_grad()
torch.backends.cudnn.benchmark

Correct answer: torch.cuda.amp.autocast()

torch.cuda.amp.autocast() automatically casts operations to FP16 where safe, enabling Tensor Core acceleration.

Question 49: When using mixed-precision training (FP16/BF16 + FP32) in a multi-GPU setting, where are the FP32 master weights typically stored?

Only on GPU 0 as a parameter server
On each GPU alongside the FP16/BF16 working copies (Correct answer)
Exclusively in CPU RAM to save GPU memory
Distributed across NVLink cache with no full copy on any GPU

Correct answer: On each GPU alongside the FP16/BF16 working copies

Each GPU maintains its own FP32 master copy for numerically stable gradient accumulation while using FP16/BF16 for forward and backward compute.

Question 50: How many GPUs can be directly interconnected in a single NVLink domain using NVIDIA's H100 SXM platform?

32 GPUs
16 GPUs
4 GPUs
8 GPUs (Correct answer)

Correct answer: 8 GPUs

H100 SXM servers connect 8 GPUs within a single NVLink domain using NVSwitch chips for all-to-all connectivity.

Question 51: What does the CUDA event timing API measure that CPU timers cannot accurately capture?

Host-to-device transfer bandwidth
GPU temperature during execution
Number of CUDA cores utilized
Precise GPU kernel execution time excluding CPU overhead (Correct answer)

Correct answer: Precise GPU kernel execution time excluding CPU overhead

CUDA events are recorded on the GPU timeline and measure actual kernel execution time without CPU-side scheduling jitter or synchronization overhead.

Question 52: Which NVIDIA technology allows network adapters to process Ethernet frames and perform RDMA operations simultaneously on the same port?

DPDK acceleration
VXLAN offload
RoCE (RDMA over Converged Ethernet) (Correct answer)
Dual-port bonding

Correct answer: RoCE (RDMA over Converged Ethernet)

RoCE enables RDMA semantics over standard Ethernet, allowing the same physical port to handle both standard Ethernet and RDMA traffic.

Question 53: A CUDA kernel uses 64 registers per thread on an SM that supports 65,536 total registers. With 1024 threads per block, how many blocks can run concurrently per SM?

8
4
2
1 (Correct answer)

Correct answer: 1

64 registers × 1024 threads = 65,536 registers per block, which exactly exhausts the SM's register budget, allowing only 1 block concurrently.

Question 54: Which kernel launch configuration parameter controls the number of threads per block?

blockDim (Correct answer)
threadIdx
blockIdx
gridDim

Correct answer: blockDim

blockDim specifies the dimensions (and thus total count) of threads within each block.

Question 55: What is backpropagation used for?

Data preprocessing.
Model deployment.
Weight updates using gradients (Correct answer)
Data visualization.

Correct answer: Weight updates using gradients

Backpropagation is a fundamental algorithm used in training artificial neural networks to efficiently calculate the gradients of the loss function with respect to the network's weights. These gradients indicate the direction and magnitude by which the weights should be adjusted to minimize the loss. By iteratively updating the weights based on these gradients, backpropagation enables the network to learn from its errors and improve its performance.

Question 56: Which technique allows overlapping CPU computation with GPU kernel execution in CUDA?

Launching kernels into non-default streams and continuing CPU work before synchronizing (Correct answer)
Enabling concurrent kernel execution via cudaSetDeviceFlags
Allocating all memory as Unified Memory
Using cudaDeviceSynchronize() immediately after each launch

Correct answer: Launching kernels into non-default streams and continuing CPU work before synchronizing

Asynchronous kernel launches into non-default streams return control to the CPU immediately, allowing CPU code to execute in parallel with GPU computation until an explicit sync is needed.

Question 57: When a NCA professional encounters an unfamiliar challenge in data center gpu solutions, what is the recommended first course of action?

Apply the solution used for the most recent similar problem without adaptation
Postpone addressing the issue indefinitely
Proceed based on personal intuition alone
Research applicable standards, consult with subject matter experts, and document the approach (Correct answer)

Correct answer: Research applicable standards, consult with subject matter experts, and document the approach

Professional practice requires a methodical approach to unfamiliar challenges: research the applicable standards, consult experts when needed, and document the reasoning for the chosen approach.

Question 58: An engineer is deploying a GPU cluster for distributed deep learning. Which NVIDIA networking solution provides the lowest latency for GPU-to-GPU communication across nodes?

10GbE with RoCE
OmniPath Fabric
NVIDIA Quantum-2 InfiniBand HDR200 (Correct answer)
25GbE Ethernet with ECMP

Correct answer: NVIDIA Quantum-2 InfiniBand HDR200

NVIDIA Quantum-2 InfiniBand delivers up to 400 Gb/s per port with ultra-low latency, making it the preferred fabric for tightly coupled distributed GPU workloads.

Question 59: What is 'sparsity' acceleration in TensorRT, and which GPU architecture first introduced hardware support for it?

Eliminating redundant batch normalization layers, enabled on Turing GPUs
Removing zero-valued activations dynamically at runtime, introduced on Volta GPUs
Exploiting 2:4 structured sparsity in weight tensors for 2× speedup, first supported on Ampere GPUs (Correct answer)
Pruning convolutional filters automatically during TensorRT build, available since Pascal

Correct answer: Exploiting 2:4 structured sparsity in weight tensors for 2× speedup, first supported on Ampere GPUs

NVIDIA's 2:4 structured sparsity (2 zeros per 4 weights) is decoded in hardware by Ampere Tensor Cores, delivering up to 2× speedup for sparse models.

Question 60: How should NCA professionals handle confidential information related to computer vision & nlp workloads?

Delete all records after project completion
Share freely with all colleagues for transparency
Store information without any security measures
Follow established protocols for data protection, access control, and disclosure in accordance with applicable regulations (Correct answer)

Correct answer: Follow established protocols for data protection, access control, and disclosure in accordance with applicable regulations

Confidential information must be handled according to established protocols, regulatory requirements, and professional ethics standards, including proper access control and disclosure procedures.

NVIDIA-Certified Associate - Data Science

The NVIDIA-Certified Associate - Data Science certification validates foundational knowledge in data science, including data manipulation, machine learning, and deep learning using NVIDIA tools and platforms.

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